Paul Merolla

My research focus is to build more intelligent computers, drawing inspiration from neuroscience, engineering, and machine learning. I have been a lead designer on more than 10 brain-inspired chips, including Stanford’s Neurogrid and IBM’s TrueNorth chip. While my main expertise is designing low-power neural hardware, I am also passionate about developing algorithms for these systems aimed at solving real world problems.

Recently, I co-founded Neuralink, a startup based in San Francisco developing a high bandwidth interface for the nervous system. Before that, I was a research scientist in IBM's Brain-Inspired Computing group (2010 - 2016), and before that, I was a postdoctoral scholar in Stanford's Brains in Silicon lab (2006 - 2010). I received my PhD from the University of Pennsylvania in Bioengineering (2006) and a BS from the University of Virginia in Electrical Engineering (2000).

Recent News

Neurogrid die
April 12th, 2017: First official press of our new venture, Neuralink!
A few weeks ago, my colleagues and I spent a lively evening chatting with Tim Urban, a journalist from Wait But Why. If you haven't come across Tim's work before, he is an incredibly gifted writer that has a knack for deconstructing complex topics. I think he's done it again: please enjoy Tim's latest feature on neuroscience and BMI.

Neurogrid die
March 28th, 2016: Our latest paper in PNAS, "Convolutional networks for fast, energy-efficient neuromorphic computing".
How can we modify deep learning to work within the constraints of low power neural network hardware? Here, we describe a modified version of backpropagation, which achieves near state of the art performance using discrete synapses, limited precision communication, and restricted connectivity. In addition to the exciting theoretical implications, we also ran our algorithm live on the TrueNorth chip, and achieved near state of the art performance on 8 datasets, running between 1200 and 2600 FPS while only using between 25 and 275 mW! See Andrej Karpathy's tweet.

TrueNorth Chip
August 8th, 2014: Our latest chip, dubbed TrueNorth, was featured on the cover of Science.
TrueNorth's architecture is inspired by the structure and function of the brain. The chip is a 64 by 64 array of lightweight neurosynaptic cores, where each core combines neurons (computation), synapses and neuron states (memory), and a spike router (communication). With 5.4 billion transistors (one of the largest chips built to date), the chip has 1 million neurons and 256 million synapses, runs in real time, and consumes less than 100mW of power. I was one of the lead chip architects.
Read the Science article (behind paywall) or pre-published version (no paywall), and the feature. Also listen to the podcast.

Neurogrid die
April 26th, 2014: Paper on Neurogrid is out in IEEE Proceedings. Shown is a photograph of a Neurocore chip.
Neurogrid is an analog neuromorphic supercomputer, made of sixteen Neurocore chips connected in a tree topology. I co-led the design, along with John Arthur, Rodrigo Alvarez, and Kwabena Boahen.

Selected Publications

[2016] Merolla. P, Appuswamy. R, et al. “Deep neural networks are robust to weight binarization and other non-linear distortions”, arXiv:1606.01981, June, 2016. Bibtex

[2014] Merolla. P, Arthur. JV, Alvarez-Icaza. R, Cassidy. A, Sawada. J, Akopyan. F, Jackson. B, et al., “A million spiking-neuron integrated circuit with a scalable communication network and interface”, Science, 668-73, August 8th, 2014. Cover with Feature Story.  Bibtex

[2014] Benjamin. BV, Gao. P, McQuinn. E, Choudhary. S, Chandrasekaran. A, Bussat. JM, Alvarez. R, Arthur. JV, Merolla. P, and Boahen. K, “Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations”, Proceedings of the IEEE, vol 102, no 5, pp 699--716, March 2014. Bibtex

[2014] Merolla. P, Arthur. J, Alvarez. R, Bussat. JM, and Boahen. K, “A Multicast Tree Router For Multichip Neuromorphic Systems”, IEEE Transactions on Circuits and Systems, vol 61, no 3, pp 820-833, March 2014. Bibtex

[2011] Merolla. P, Arthur. J, Akopyan. F, Imam. N, Manohar. R, and Modha. D, “A Digital Neurosynaptic Core using Embedded Crossbar Memory with 45pJ per spike in 45nm”, IEEE Custom Integrated Circuits Conference, September 2011. Bibtex

[2010] Merolla. P, Ursell. T, and Arthur. JV, “The Thermodynamic Temperature of a Rhythmic Spiking Network”, arXiv:1009.5473, September, 2010. Bibtex